1. Field of the Invention
The present invention relates to a sensing amplifier circuit, and more particularly, to a sensing amplifier operated with a smaller sensing current difference.
2. Description of the Related Art
FIG. 1 schematically shows a circuit diagram of a conventional sensing amplifier. Referring to FIG. 1, the conventional sensing amplifier comprises a program memory cell 105, an erase memory cell 109, two NMOS transistors 101 and 103, and two inverters 113 and 115 served as a latch. Wherein, the program memory cell 105 provides a first driving current ION based on a bit data, and the erase memory cell 109 provides a second driving current IOFF based on the bit data.
As shown in FIG. 1, a first source/drain of the NMOS transistor 101 is grounded, a gate is electrically coupled to a control signal RE, a second source/drain is electrically coupled to an input terminal of the inverter 113, an output terminal of the inverter 115 and the program memory cell 105.
Similarly, a first source/drain of the NMOS transistor 103 is grounded, a gate is electrically coupled to the control signal RE, a second source/drain is electrically coupled to an output terminal of the inverter 113, an input terminal of the inverter 115 and the erase memory cell 109.
When the control signal RE is enabled, the NMOS transistors 101 and 103 are both turned on, thus the potential on the nodes N1 and N2 are pulled down to a ground level. Meanwhile, both the program memory cell 105 and the erase memory cell 109 are enabled to generate the program memory cell current ION and the erase memory cell current IOFF respectively. The program current ION and the erase current IOFF both accumulate the electric charges on the nodes N1 and N2. It is assumed that the greater the program current ION, the faster the accumulation speed on the node N1. Thus, the inverter 113 is driven and the potential on the node N2 is pulled down to a potential of logic 0, and vice versa.
FIG. 2 schematically shows a circuit diagram of an inverter suitable for the inverters 113 and 115 of FIG. 1. Referring to FIG. 2, a general inverter circuit comprises an NMOS transistor 201 and a PMOS transistor 203. Wherein, a first source/drain of the NMOS transistor 201 is grounded, and a gate is electrically coupled to an input terminal A1 of the inverter. A first source/drain and a gate of the PMOS transistor 203 are electrically coupled to a second source/drain and the gate of the NMOS transistor 201, respectively. In addition, a second/source of the PMOS transistor 203 is electrically coupled to a positive DC bias. Wherein, the second source/drain of the NMOS transistor 201 and the first source/drain of the PMOS transistor 203 are electrically coupled to an output terminal A2 of the inverter.
Referring to FIGS. 1 and 2, in the conventional sensing amplifier, when the transistors 101 and 103 are turned on and the potential on the nodes N1 and N2 are pulled down to the ground level, the program memory cell current ION and the erase memory cell current IOFF will accumulate the electric charges on the nodes N1 and N2. Moreover, the PMOS transistor (e.g. the PMOS transistor 203) in the inverters 113 and 115 will generate a drain current, which also accumulates the electric charges on the nodes N1 and N2. Accordingly, it is required to increase the current difference between the program memory cell current ION and the erase memory cell current IOFF in order to drive the inverters 113 and 115.
In addition, while accumulating the electric charges on the nodes N1 and N2, if noise interference occurs, the inverters 113 and 115 both easily fail to operate due to the impact of the noise.